`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:32:07 04/04/2013 
// Design Name: 
// Module Name:    FPGA_top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module FPGA_top(
	input clk_100MHz,
	input reset,
	input go,
	input load,
	input sw7,
	input sw6,
	input sw5,
	input sw4,
	input sw3,
	input sw2,
	input sw1,
	input sw0,
	output [03:00] dis_control,  
   output [06:00] led_dis,
	output full_led,
	output empty_led
    );
	assign reset_right =  reset;//~reset; check this
	 wire go_pos_edge, load_posedge, pop, clk_50MHz, display_success, read_pulse;
	 wire [7:0] Latched_Data;
	 wire [7:0] o_rdata;
	 wire [15:0] seg_data;
	 
	GoButton Go (.go_b(go), .clk(clk_100MHz), .reset_b(reset_right), .positive_edge(go_pos_edge));
	LoadButton Load (.clk(clk_100MHz), .BTND(load), .reset_b(reset_right), .pos_edge(load_pos_edge));
	SwitchLatcher SL (.clk(clk_100MHz), .SW0(sw0), .SW1(sw1), .SW2(sw2), .SW3(sw3), .SW4(sw4), .SW5(sw5), .SW6(sw6), .SW7(sw7), .reset_b(reset_right), .latched_data(Latched_Data));
	ExecutionControl EC(.go(go_pos_edge), .clk(clk_100MHz), .tx_successful(display_success), .stop(is_empty), .pop_data(pop));
	Asynchronous_FIFO FIFO(.push(load_pos_edge), .pop(pop), .wdata(Latched_Data), .wclk(clk_100MHz), .rclk(clk_50MHz), .rdata(o_rdata), .full(full_led), .empty(empty_led));
	//slowclock clockdivider (.clk(clk_100MHz), .clk_50MHz(clk_50MHz));
	clockdivider clkdiv(.clk(clk_100MHz), .clk_50MHz(clk_50MHz));
	CPU cpu1(.inst_ex(pop), .inst_data(o_rdata), .reset_b(reset_right), .clk_50Mhz(clk_50MHz), .reg_read(read_pulse), .reg_data(seg_data));
	seg_display seg7 (.clk_50MHz(clk_50MHz), .reset_b(reset_right), .dis_control(dis_control), .led_dis(led_dis), .read_data(seg_data), .read_pulse(read_pulse));
	
endmodule

